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IDT74FCT16646AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 16-BIT BUS TRANSCEIVER/ REGISTER (3-STATE)
FEATURES:
* * * * * * * *
IDT74FCT16646AT/CT/ET
DESCRIPTION:
0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1A (max.) VCC = 5V 10% High drive outputs (-32mA IOH, 64mA IOL) Power off disable outputs permit "live insertion" Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25C * Available in SSOP and TSSOP packages
The FCT16646T 16-bit registered transceiver is built using advanced dual metal CMOS technology. These high-speed, low-power devices are organized as two independent 8-bit bus transceivers with 3-state D-type registers. The control circuitry is organized for multiplexed transmission of data between A bus and B bus either directly or from the internal storage registers. Each 8-bit transceiver/register features direction control (xDIR), over-riding Output Enable control (xOE) and Select lines (xSAB and xSBA) to select either real-time data or stored data. Separate clock inputs are provided for A and B port registers. Data on the A or B data bus, or both, can be stored in the internal registers by the low-to-high transitions at the appropriate clock pins. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16646T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.
FUNCTIONAL BLOCK DIAGRAM
1O E 1DIR
2O E 2DIR
1CLK BA 1SB A 1CLK AB 1SA B B R EG
2CLK BA 2S BA 2CLK AB 2S AB B R EG
D C
1A 1 A R EG 1B 1 2A 1 A RE G
D C
2B 1
D C
D C
TO S EVE N O THE R C HAN NEL S
TO S EVE N O THE R C HAN NELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2002 Integrated Device Technology, Inc.
JUNE 2002
DSC-5448/3
IDT74FCT16646AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1DIR
1CLKAB 1SAB
ABSOLUTE MAXIMUM RATINGS(1)
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Symbol
1OE 1CLKBA 1SBA
Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current
Max -0.5 to +7 -0.5 to VCC+0.5 -65 to +150 -60 to +120
Unit V V C mA
VTERM(2) TSTG IOUT
VTERM(3) Terminal Voltage with Respect to GND
GND
1A1 1A2
GND
1B1 1B2
VCC
1A3 1A4 1A5
VCC
1B3 1B4 1B5
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals for FCT162XXX.
GND
1A6 1A7 1A8 2A1 2A2 2A3
GND
1B6 1B7 1B8 2B1 2B2 2B3
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF
GND
2A4 2A5 2A6
GND
2B4 2B5 2B6
NOTE: 1. This parameter is measured at characterization but not tested.
VCC
2A7 2A8
VCC
2B7 2B8
PIN DESCRIPTION
Pin Names xAx xBx xCLKAB, xCLKBA xSAB, xSBA xDIR, xOE Description Data Register A Inputs Data Register B Outputs Data Register B Inputs Data Register A Outputs Clock Pulse Inputs Output Data Source Select Inputs Output Enable Inputs
GND
2SAB 2CLKAB 2DIR
GND
2SBA 2CLKBA 2OE
SSOP/ TSSOP TOP VIEW
FUNCTION TABLE(1)
Inputs xOE H H L L L L xDIR X X L L H L xCLKAB H or L X X X H or L xCLKBA H or L X H or L X X xSAB X X X X L H xSBA X X L H X X Input Output Output Input xAx Input Data I/O(2) xBx Input Isolation Store A and B Data Real Time B Data to A Bus Stored B Data to A Bus Real Time A Data to B Bus Stored A Data to B Bus Operation or Function
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance 2. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
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IDT74FCT16646AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
BUS A
BUS B
BUS A
BUS B
xD IR
xO E
xC LKAB
xC LKBA
xSA B
xSB A
xD IR
xOE
xC LKAB
xC LKBA
xSA B
xSB A
L
L
X
X
X
L
H
L
X
X
L
X
REAL-TIME TRANSFER BUS B TO A
REAL-TIME TRANSFER BUS A TO B
BUS A
BUS B
BUS A
BUS B
xD IR
xO E
xC LKAB
xC LKBA
xSA B
xSB A
xD IR
(1)
xOE
xC LKAB
xC LKBA
xSA B
xSB A
H L X
L L H
X

X X X
X X X
L H
L L
X H or L
H or L X
X H
H X
X
STORAGE FROM A AND/OR B
TRANSFER STORED DATA TO A AND/OR B
NOTE: 1. Cannot transfer data to A bus and B bus simultaniously.
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IDT74FCT16646AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 10%
Symbol VIH VIL IIH IIL IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) Input LOW Current (Input pins)(5) Input LOW Current (I/O pins)(5) High Impedance Output Current (3-State Output pins)(5) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC VCC = Min., IIN = -18mA VCC = Max., VO = GND(3) -- VCC = Max. VO = 2.7V VO = 0.5V VI = GND Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC Min. 2 -- -- -- -- -- -- -- -- -80 -- -- Typ.(2) -- -- -- -- -- -- -- -- -0.7 -140 100 5 Max. -- 0.8 1 1 1 1 1 1 -1.2 -250 -- 500 V mA mV A A Unit V V A
OUTPUT DRIVE CHARACTERISTICS
Symbol IO VOH Parameter Output Drive Current Output HIGH Voltage VCC = Max., VO = VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL VCC = 0V, VIN or VO 4.5V Test Conditions(1) 2.5V(3) IOH = -3mA IOH = -15mA IOH = -32mA(4) IOL = 64mA Min. -50 2.5 2.4 2 -- -- Typ.(2) -- 3.5 3.5 3 0.2 -- Max. -180 -- -- -- 0.55 1 Unit mA V V A
VOH IOFF
Output LOW Voltage Input/Output Power Off Leakage(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is 5A at TA = -55C.
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IDT74FCT16646AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max., Outputs Open xOE = xDIR = GND One Input Toggling 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (xCLKBA) 50% Duty Cycle xOE = xDIR = GND fi = 5MHz 50% Duty Cycle One Bit Toggling VCC = Max., Outputs Open fCP = 10MHz (xCLKBA) 50% Duty Cycle xOE = xDIR = GND Sixteen Bits Toggling fi = 2.5MHz 50% Duty Cycle Min. -- -- Typ.(2) 0.5 75 Max. 1.5 120 Unit mA A/ MHz
VIN = VCC VIN = GND
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
0.8
1.7
mA
VIN = 3.4V VIN = GND
--
1.3
3.2
VIN = VCC VIN = GND
--
3.8
6.5(5)
VIN = 3.4V VIN = GND
--
8.3
20(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
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IDT74FCT16646AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16646AT Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tSU tH tW tSK(o) Parameter Propagation Delay Bus to Bus Output Enable Time xDIR or xOE to Bus Output Disable Time xDIR or xOE to Bus Propagation Delay Clock to Bus Propagation Delay xSBA or xSAB to Bus Set-up Time HIGH or LOW, Bus to Clock Hold Time HIGH or LOW, Bus to Clock Clock Pulse Width HIGH or LOW Output Skew(3) Condition(1) CL = 50pF RL = 500 Min.(2) 2 2 2 2 2 2 1.5 5 -- Max. 6.3 9.8 6.3 6.3 7.7 -- -- -- 0.5 FCT16646CT Min.(2) 1.5 1.5 1.5 1.5 1.5 2 1.5 5 -- Max. 5.4 7.8 6.3 5.7 6.2 -- -- -- 0.5 FCT16646ET Min.(2) 1.5 1.5 1.5 1.5 1.5 2 0 3(4) -- Max. 3.8 4.8 4 3.8 4.2 -- -- -- 0.5 Unit ns ns ns ns ns ns ns ns ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. 4. This limit is guaranteed but not tested.
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IDT74FCT16646AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 7.0V 500 V IN Pulse Generator D.U.T. 50pF RT 500 CL V OUT
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
DATA INPUT tSU TIM ING INPUT ASYNCHRONOUS CONTROL PRES ET CLEA R ETC. SYNCHRONOUS CONTROL PRES ET CLEA R CLOCK ENABLE ETC. tREM
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE
1.5V
1.5V
tSU
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE SAM E PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE P HASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V DISABLE 3V CONTROL INPUT tPZL OUTPUT NORM ALLY LOW SW ITCH CLOSED tPZH OUTPUT NORM ALLY HIGH SW ITCH OPEN 3.5V 1.5V 0.3V tPHZ 0.3V 1.5V 0V 0V VOH tPLZ 1.5V 0V 3.5V VOL
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT74FCT16646AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX FCT Temp. Range XXX Family XXXX Device Type XX Package
PV PA
Shrink Small Outline Package Thin Shrink Small Outline Package
646AT 16-Bit Bus Transceiver/Register 646CT 646ET
16
Double-Density, 5 Volt, High Drive
74
- 40C to +85C
DATA SHEET DOCUMENT HISTORY
5/21/2002 6/21/2002 Removed TVSOP package Updated according to PDNs Logic-00-07 and Logic-01-04
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
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for Tech Support: logichelp@idt.com (408) 654-6459
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